1. Field of the Invention
The present invention relates to an array substrate for a liquid crystal display (LCD) and its fabrication method, and more particularly, to an array substrate for an LCD and its fabrication method capable of improving electrical characteristics of thin film transistors by improving ON-current and electric charge mobility.
2. Discussion of the Related Art
As the consumer interest in information displays is growing and the demand for portable (mobile) information devices is increasing, research and commercialization of light and thin flat panel displays (“FPD”) have increased. Among FPDs, the liquid crystal display (“LCD”) is a device for displaying images by using optical anisotropy of liquid crystals. LCD devices exhibit excellent resolution, color, and picture quality. As a result, LCD devices are widely used in notebook computers, desktop monitors, and the like.
The LCD includes a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate. The general structure of the LCD according to the related art will now be described in detail with reference to FIG. 1.
FIG. 1 is an exploded perspective view showing a general LCD according to the related art. As shown in FIG. 1, the LCD includes a color filter substrate 5, an array substrate 10, and a liquid crystal layer 30 formed between the color filter substrate 5 and the array substrate 10. The color filter substrate 5 includes a color filter (C) including a plurality of sub-color filters 7 that implement red, green, and blue colors, a black matrix 6 for dividing the sub-color filters 7 and blocking light transmission through the liquid crystal layer 30, and a transparent common electrode 8 for applying voltage to the liquid crystal layer 30. The array substrate 10 includes gate lines 16 and data lines 17 which are arranged horizontally and vertically, respectively to define a plurality of pixel regions (P), TFTs, or switching elements, formed at respective crossings of the gate lines 16 and the data lines 17, and pixel electrodes 18 formed on the pixel regions (P). The color filter substrate 5 and the array substrate 10 are attached in a facing manner by a sealant (not shown) formed at an edge of an image display region to form a liquid crystal panel, and the color filter substrate 5 and the array substrate 10 are attached to each other by an attachment key formed on the color filter substrate 5 or the array substrate 10.
In the fabricating process of the LCD, a plurality of masking processes (e.g., photographing processes) are performed to fabricate the array substrate including the TFTs, so a method for reducing the number of masks is required to improve productivity.
FIGS. 2A to 2E are sectional views sequentially showing a fabrication process of the array substrate of the LCD in FIG. 1 according to the related art. As shown in FIG. 2A, a gate electrode 21 made of a conductive material is formed by using a photolithography process (e.g., a first masking process) on a substrate. Next, as shown in 2B, a first insulation film 15a, an amorphous silicon thin film, and an n+ amorphous silicon thin film are sequentially deposited on the entire surface of the substrate 10 with the gate electrode 21 formed thereon, and the amorphous silicon thin film and the n+ amorphous silicon thin film are selectively patterned by using the photolithography process (e.g., a second masking process) to form an active pattern 24 formed of the amorphous silicon thin film on the gate electrode 21. In this case, the n+ amorphous silicon thin film pattern 25, which has been patterned in the same form as the active pattern 24, is formed on the active pattern 24.
Thereafter, as shown in FIG. 2C, a conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned by using the photolithography process (e.g., a third masking process) to form a source electrode 22 and a drain electrode 23 at an upper portion of the active pattern 24. At this time; a certain portion of the n+ amorphous silicon thin film pattern formed on the active pattern 24 is removed through the third masking process to form an ohmic-contact layer 25n between the active pattern 24 and the source and drain electrodes 22 and 23.
Subsequently, as shown in FIG. 2D, a passivation layer 15b is deposited on the entire surface of the array substrate 10 with the source electrode 22 and the drain electrode 23 formed thereon, and a portion of the passivation layer 15b is removed through the photolithography process (e.g., a fourth masking process) to form a contact hole 40 exposing a portion of the drain electrode 23. Finally, as shown in FIG. 2E, a transparent conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned by using the photolithography process (e.g., a fifth making process) to form a pixel electrode 18 electrically connected with the drain electrode 23 via the contact hole 40.
As mentioned above, in fabricating the array substrate including the TFTs, five photolithography process are necessarily performed to pattern the gate electrode, the active layer, the source and drain electrodes, the contact hole, and the pixel electrode. The photolithography process is a process of transferring a pattern formed on a mask onto the substrate on which a thin film is deposited to form a desired pattern, which includes a plurality of processes such as a process of coating a photosensitive solution, an exposing process, a developing process, etc. The plurality of photolithography processes degrade production yield.
FIG. 3 is a sectional view schematically showing the structure of a general thin film transistor according to the related art. With reference to FIG. 3, after the active layer 24 is deposited, a channel part is formed through a back channel etch, namely, an etching process. In this case, current flows through the metal electrode of the source electrode 22, the ohmic-contact layer 25n, the channel layer of the active layer 24, the ohmic-contact layer 25n, and then to the metal electrode of the drain electrode 23 (A→B→C→D). In this case, there is an electrical barrier between the channel layer of the active layer 24 and the ohmic-contact layer 25n (A˜B, C˜D), interfering with the flow of electrons and increasing resistance. Reference letter “d” indicates the depth of the etched portion, and “Vs,” “Vd,” and “Vg” indicate a source voltage, a drain voltage, and a gate voltage, respectively.
Thus, linear electron mobility of the TFTs is reduced due to a vertical serial resistance at the linear region. In addition, the active layer has intrinsic characteristics, such as a Vth value, namely, a threshold voltage ranging from 1V to 2V causing a problem that when the panel is driven, the gate voltage should be applied according to the threshold voltage Vth to activate the TFT. However, there is no technique for moving the threshold voltage Vth value.